An array of memory cells is typically divided into banks of memory, with each of the banks further divided into sections of memory. The memory cells are typically arranged in rows and columns of memory, with a row of memory cells coupled to a respective word line. The columns of memory are coupled to sense amplifiers that sense data from accessed memory cells and amplify the sensed data to be provided over a read data path during read operations. The sense amplifiers are also used during write operations to capture the write data to be written to the memory cells. When selecting memory to access, row and column memory addresses are provided to row and column address decoders. The row decoders activate the word lines of the rows corresponding to the row address. Sense amplifiers are activated and data from the memory cells of the activated word lines are sensed and amplified. The data can be provided to the read data path for read operations or data can be written through the sense amplifiers to the memory cells of the selected rows.
FIG. 1 illustrates a portion 100 of a bank of memory. The portion 100 includes memory sections 110 and sense amplifier gaps 120 in which sense amplifiers shared by adjacent memory sections 110 are located. Row decoder and sense amplifier gap control logic coupled to the memory sections 110 and to sense amplifiers in the sense amplifier gaps 120 are used when accessing memory of the memory sections 110. As illustrated by the detailed section 160, row decoders 140 and sense amplifier gap control logic 130 are associated with respective memory sections 110 and sense amplifier gaps 120. The row decoders 140 selectively activate word lines of the respective memory section and the sense amplifier gap control logic 150 controls operation of the sense amplifiers located in the associated sense amplifier gaps 120 when memory cells of a respective memory section are accessed. Internal memory section address signals SEC1of8, SEC10f4 derived from the memory addresses of memory to be accessed are provided to the row decoders 140 and the sense amplifier gap control logic 150 to identify the memory sections to be accessed. In response to the SEC1of8, SEC1of4 signals indicating access to a particular memory section 110, the associated row decoder 140 and sense amplifier gap control logic 150 are used to carry out the access operation.
Circuits of the row decoders 140 and the sense amplifier gap control logic 150 are electrically connected to a voltage supply that provides power to the circuits. As known, however, even when the circuits of the row decoders 140 and the sense amplifier gap control logic 150 are not operating, for example, a memory access operation is not being performed, the circuits consume power due to leakage currents. A typical measure of power consumption while a memory is not operating is “standby current.” The leakage currents result from the voltage difference between the voltage supply and ground that is placed across the circuits of the row decoders 140 and the sense amplifier gap control logic 150. The leakage currents for the individual circuits may be minor. The total leakage current for the circuits of all of the row decoders 140 and sense amplifier gap control logic 150 of a memory array, however, can nevertheless result in a sum power consumption that may be significant, especially when considering the memory is not operating. In many low power applications, such as in portable electronic systems that rely on battery power, reducing power consumption by the memory, including that consumed by the memory during “standby,” is desirable.